Mapping for better than worst-case delays in LUT-based FPGA designs

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Authors: Kirill Minkovich UCLA, Los Angeles, CA
Jason Cong UCLA, Los Angeles, CA
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· Proceeding
FPGA '08 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Pages 56-64
ACM New York, NY, USA ©2008
table of contents ISBN: 978-1-59593-934-0 doi>10.1145/1344671.1344681
Mapping for better than worst-case delays in LUT-based FPGA designs Published by ACM 2008 Article
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