Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

doi:10.1145/1344671.1344699

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

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Authors:	Alessandro Cevrero	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Panagiotis Athanasopoulos	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Hadi Parandeh-Afshar	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Ajay K. Verma	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Philip Brisk	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Frank K. Gurkaynak	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Yusuf Leblebici	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland
	Paolo Ienne	Swiss Federal Institute of Technology: Lausanne (EPFL), Lausanne, Switzerland

	2008 Article
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	· Proceeding
	FPGA '08 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
	Pages 181-190 ACM New York, NY, USA ©2008 table of contents ISBN: 978-1-59593-934-0 doi>10.1145/1344671.1344699

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