FPGA interconnect design using logical effort

Authors: Haile Yu The Chinese University of Hong Kong, Shatin, Hong Kong
Yuk Hei Chan The Chinese University of Hong Kong, Shatin, Hong Kong
Philip H.W. Leong The Chinese University of Hong Kong, Shatin, Hong Kong
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· Proceeding
FPGA '08 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Pages 257-257
ACM New York, NY, USA ©2008
table of contents ISBN: 978-1-59593-934-0 doi>10.1145/1344671.1344710
FPGA interconnect design using logical effort Published by ACM 2008 Article
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