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The minimization of hardware size in reconfigurable embedded platforms
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Authors:
Nei-Chiung Perng
Genesys Logic, Inc.
Jian-Jia Chen
Swiss Federal Institute of Technology Zurich (ETHZ)
Tei-Wei Kuo
National Taiwan University
Published in:
· Proceeding
SAC '08
Proceedings of the 2008 ACM symposium on Applied computing
ACM
New York, NY
, USA
©2008
table of contents
ISBN: 978-1-59593-753-7
doi>
10.1145/1363686.1364041
2008 Article
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· Downloads (12 Months): 10
· Citation Count: 0
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Upcoming Conference:
SAC 2012
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Tags:
algorithms
computer-aided design
design
design management
dynamically reconfiguration
fpga
gate arrays
performance
scheduling
sequencing and scheduling
theory
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