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Pipelined network of PLA based circuit design
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Authors:
Suganth Paul
Intel Corporation, Austin, TX, USA
Rajesh Garg
Texas A&M University, College Station, TX, USA
Sunil P. Khatri
Texas A&M University, College Station, TX, USA
Published in:
· Proceeding
GLSVLSI '08
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Pages 213-218
ACM
New York, NY
, USA
©2008
table of contents
ISBN: 978-1-59593-999-9
doi>
10.1145/1366110.1366162
2008 Article
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Tags:
design
pipelining
pla
synchronous
vlsi
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