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Evolution of synthetic RTL benchmark circuits with predefined testability

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Authors: Tomas Pecenka ON Semiconductor, Roznov pod Radhostem, Czech Republic
Lukas Sekanina Brno University of Technology, Brno, Czech Republic
Zdenek Kotasek Brno University of Technology, Brno, Czech Republic
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· Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES) TODAES Homepage archive
Volume 13 Issue 3, July 2008
ACM New York, NY, USA
table of contents doi>10.1145/1367045.1367063
Evolution of synthetic RTL benchmark circuits with predefined testability Published by ACM 2008 Article
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· Citation Count: 4


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