SIGN IN
SIGN UP
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Full Text:
PDF
Buy this Article
Authors:
Min Ni
Northwestern University, IL
Seda Ogrenci Memik
Northwestern University, IL
Published in:
· Proceeding
DAC '08
Proceedings of the 45th annual Design Automation Conference
Pages 610-613
ACM
New York, NY
, USA
©2008
table of contents
ISBN: 978-1-60558-115-6
doi>
10.1145/1391469.1391625
2008 Article
Bibliometrics
· Downloads (6 Weeks): 3
· Downloads (12 Months): 15
· Downloads (cumulative): 189
· Citation Count: 3
Tools and Resources
Buy this Article
Request Permissions
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
DAC '13
Share:
|
Tags:
algorithms
clock skew scheduling
design
design aids
dual-vth
gate sizing
leakage power optimization
performance
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder