Automated transistor sizing for FPGA architecture exploration

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Authors: Ian Kuon University of Toronto, Toronto, Ontario, Canada
Jonathan Rose University of Toronto, Toronto, Ontario, Canada
Published in:
· Proceeding
DAC '08 Proceedings of the 45th annual Design Automation Conference
Pages 792-795
ACM New York, NY, USA ©2008
table of contents ISBN: 978-1-60558-115-6 doi>10.1145/1391469.1391671
Automated transistor sizing for FPGA architecture exploration Published by ACM 2008 Article
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· Citation Count: 7


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