DVFS in loop accelerators using BLADES

doi:10.1145/1391469.1391694

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DVFS in loop accelerators using BLADES

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Authors:	Ganesh Dasika	University of Michigan - Ann Arbor, Ml
	Shidhartha Das	ARM, Ltd., Cambridge, United Kingdom
	Kevin Fan	University of Michigan - Ann Arbor, Ml
	Scott Mahlke	University of Michigan - Ann Arbor, Ml
	David Bull	ARM, Ltd., Cambridge, United Kingdom

	2008 Article
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DAC '08 Proceedings of the 45th annual Design Automation Conference

ACM New York, NY, USA ©2008
table of contents ISBN: 978-1-60558-115-6 doi>10.1145/1391469.1391694

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Tags: design embedded systems frequency scaling high-level synthesis low power microprocessors and microcomputers performance voltage scaling

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