Increasing minimum operating voltage (V DDmin ) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

Increasing minimum operating voltage (V_DDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

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Authors:	Taro Niiyama	University of Tokyo, Tokyo, Japan
	Zhe Piao	University of Tokyo, Tokyo, Japan
	Koichi Ishida	University of Tokyo, Tokyo, Japan
	Masami Murakata	STARC, Yokohama, Japan
	Makoto Takamiya	University of Tokyo, Tokyo, Japan
	Takayasu Sakurai	University of Tokyo, Tokyo, Japan

	2008 Article
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Published in:

	· Proceeding
	ISLPED '08 Proceedings of the 13th international symposium on Low power electronics and design
	Pages 117-122 ACM New York, NY, USA ©2008 table of contents ISBN: 978-1-60558-109-5 doi>10.1145/1393921.1393952

Tags: design experimentation general logic measurement minimum operating voltage performance reliability subthreshold variations