Penalty for power reduction -: performance or schedule or yield?

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Authors:	Bodhisatya Sarker	Cadence Design Systems (I) Pvt Ltd, Delhi, India
	Jaswinder Ahuja	Cadence Design Systems (I) Pvt Ltd, Delhi, India
	Arijit Dutta	Freescale Semiconductors, Bangalore, India
	Srinath D.	Kawasaki Micro, Bangalore, India
	Kaip Sridhar	Marvel Technologies, Bangalore, India
	Radhakrishnan Nair	SanDisk India, Bangalore, India
	Jayant Lahiri	ARM India, Bangalore, India

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	· Proceeding
	ISLPED '08 Proceedings of the 13th international symposium on Low power electronics and design
	ACM New York, NY, USA ©2008 table of contents ISBN: 978-1-60558-109-5 doi>10.1145/1393921.1393999

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