Clock gating for power optimization in ASIC design cycle theory & practice

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Authors: Jairam S Texas Instruments, Bangalore, India
Madhusudan Rao Texas Instruments, Bangalore, India
Jithendra Srinivas Texas Instruments, Bangalore, India
Parimala Vishwanath Texas Instruments, Bangalore, Iceland
Udayakumar H Texas Instruments, Bangalore, India
Jagdish Rao Texas Instruments, Bangalore, India
Clock gating for power optimization in ASIC design cycle theory & practice Published by ACM 2008 Article
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ISLPED '08 Proceedings of the 13th international symposium on Low power electronics and design
Pages 307-308
ACM New York, NY, USA ©2008
table of contents ISBN: 978-1-60558-109-5 doi>10.1145/1393921.1394003

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