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Thread fusion
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Authors:
José González
UPC-Intel Lab Barcelona, Barcelona, Spain
Qiong Cai
UPC-Intel Lab Barcelona, Barcelona, Spain
Pedro Chaparro
UPC-Intel Lab Barcelona, Barcelona, Spain
Grigorios Magklis
UPC-Intel Lab Barcelona, Barcelona, Spain
Ryan Rakvic
United States Naval Academy, Annapolis, Annapolis, MD, USA
Antonio González
UPC-Intel Lab Barcelona, Barcelona, Spain
2008 Article
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Published in:
· Proceeding
ISLPED '08
Proceedings of the 13th international symposium on Low power electronics and design
Pages 363-368
ACM
New York, NY
, USA
©2008
table of contents
ISBN: 978-1-60558-109-5
doi>
10.1145/1393921.1394018
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Tags:
chip multi-processor
computer architecture
design
energy-aware
in-order pipeline
low-power
microarchitecture
multi-threaded application
multiple data stream architectures
performance
thread fusion
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