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Lazy instruction scheduling: keeping performance, reducing power
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Authors:
Ali Mahjur
Shahid Beheshti University, Tehran, Iran
Mahmud Taghizadeh
Sharif University of Technology, Tehran, Iran
Amir Hossein Jahangir
Sharif University of Technology, Tehran, Iran
Published in:
· Proceeding
ISLPED '08
Proceedings of the 13th international symposium on Low power electronics and design
ACM
New York, NY
, USA
©2008
table of contents
ISBN: 978-1-60558-109-5
doi>
10.1145/1393921.1394020
2008 Article
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· Downloads (12 Months): 16
· Citation Count: 0
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Tags:
compilers
dead instruction elimination
dynamic instruction scheduling
microarchitecture
risc/cisc, vliw architectures
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