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Lens aberration aware placement for timing yield
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Authors:
Andrew B. Kahng
University of California at San Diego
Chul-Hong Park
University of California at San Diego
Puneet Sharma
Freescale Semiconductor, Inc.
Qinke Wang
Magma Design Automation, Inc.
2009 Article
Research
Refereed
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
TODAES Homepage
archive
Volume 14 Issue 1, January 2009
Article No. 16
ACM
New York, NY
, USA
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doi>
10.1145/1455229.1455245
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Tags:
algorithms
design
design for manufacturing
layout
layout
lithography
performance
timing yield
verification
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