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A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications
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Authors:
Chih-Da Chien
National Chung Cheng University
Cheng-An Chien
National Chung Cheng University
Jui-Chin Chu
National Chung Cheng University
Jiun-In Guo
National Chung Cheng University
Ching-Hwa Cheng
Feng-Chia University
2009 Article
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
TODAES Homepage
archive
Volume 14 Issue 1, January 2009
ACM
New York, NY
, USA
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doi>
10.1145/1455229.1455246
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Tags:
algorithms implemented in hardware
design
h.264
mpeg
video decoder
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