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Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
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Authors:
Gunar Schirner
University of California, Irvine, CA, USA
Rainer Dömer
University of California, Irvine, CA, USA
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· Journal
ACM Transactions on Embedded Computing Systems (TECS)
TECS Homepage
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Volume 8 Issue 1, December 2008
Article No. 4
ACM
New York, NY
, USA
table of contents
doi>
10.1145/1457246.1457250
2009 Article
Research
Refereed
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· Citation Count: 2
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Tags:
design
model validation and analysis
system level design
system-on-chip
transaction level modeling
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