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Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
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Authors:
Scott Y. L. Chin
University of British Columbia
Steven J. E. Wilton
University of British Columbia
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· Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
TRETS Homepage
archive
Volume 1 Issue 4, January 2009
ACM
New York, NY
, USA
table of contents
doi>
10.1145/1462586.1462587
2009 Article
Research
Refereed
Bibliometrics
· Downloads (6 Weeks): 6
· Downloads (12 Months): 39
· Citation Count: 0
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Tags:
algorithms
cad
design
fpga
memory
performance
placement and routing
routing
scalability
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