Clock power reduction for virtex-5 FPGAs

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Authors: Qiang Wang Xilinx, Inc., San Jose, CA, USA
Subodh Gupta Xilinx, Inc., San Jose, CA, USA
Jason H. Anderson University of Toronto, Toronto, ON, Canada
Published in:
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· Proceeding
FPGA '09 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Pages 13-22
ACM New York, NY, USA ©2009
table of contents ISBN: 978-1-60558-410-2 doi>10.1145/1508128.1508132
Clock power reduction for virtex-5 FPGAs Published by ACM 2009 Article
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