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High-performance, energy-efficient platforms using in-socket FPGA accelerators
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Authors:
Liu Ling
Intel, Beijing, China
Neal Oliver
Intel, Portland, OR, USA
Chitlur Bhushan
Intel, Portland, USA
Wang Qigang
Intel, Beijing, China
Alvin Chen
Intel, Beijing, China
Shen Wenbo
Intel, Beijing, China
Yu Zhihong
Intel, Beijing, China
Arthur Sheiman
Intel, Portland, USA
Ian McCallum
Intel, Portland, USA
Joseph Grecco
Intel, Portland, USA
Henry Mitchel
Intel, Portland, USA
Liu Dong
Intel, Beijing, China
Prabhat Gupta
Intel, Portland, USA
2009 Article
Short paper
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· Downloads (12 Months): 61
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Published in:
· Proceeding
FPGA '09
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-410-2
doi>
10.1145/1508128.1508172
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FPGA '12
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Tags:
adaptable architectures
agility
capability architectures
design
fpga
in-socket accelerator
pipeline processors
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