3D configuration caching for 2D FPGAs

doi:10.1145/1508128.1508205

3D configuration caching for 2D FPGAs

Authors:	Alessandro Cevrero	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Panagiotis Athanasopoulos	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Hadi Parandeh-Afshar	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Philip Brisk	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Yusuf Lebebici	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Paolo Ienne	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
	Maurizio Skerlj	Qimonda AG, Munich, Germany

	2009 Article Poster
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Published in:

	· Proceeding
	FPGA '09 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
	Pages 286-286 ACM New York, NY, USA ©2009 table of contents ISBN: 978-1-60558-410-2 doi>10.1145/1508128.1508205

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Tags: 3d integration configuration caching design design styles dynamic memory field programmable gate array performance reconfigurable computing

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