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top of pageABSTRACT

Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly execute a single software thread, providing very high coverage from many difference sources of faults. This reliability, however, comes at a high price in terms of per-thread IPC and overall system throughput.

We make the observation that a user may want to run both applications requiring high reliability, such as financial software, and more fault tolerant applications requiring high performance, such as media or web software, on the same machine at the same time. Yet a traditional DMR system must fully operate in redundant mode whenever any application requires high reliability.

This paper proposes a Mixed-Mode Multicore (MMM), which enables most applications, including the system software, to run with high reliability in DMR mode, while applications that need high performance can avoid the penalty of DMR. Though conceptually simple, two key challenges arise: 1) care must be taken to protect reliable applications from any faults occurring to applications running in high performance mode, and 2) the desire to execute additional independent software threads for a performance application complicates the scheduling of computation to cores. After solving these issues, an MMM is shown to improve overall system performance, compared to a traditional DMR system, by approximately 2X when one reliable and one performance application are concurrently executing.

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Author image not provided  Philip M. Wells

No contact information provided yet.

Bibliometrics: publication history
Publication years1983-2012
Publication count10
Citation Count129
Available for download7
Downloads (6 Weeks)23
Downloads (12 Months)280
Downloads (cumulative)6,536
Average downloads per article933.71
Average citations per article12.90
View colleagues of Philip M. Wells


Author image not provided  Koushik Chakraborty

No contact information provided yet.

Bibliometrics: publication history
Publication years2006-2016
Publication count36
Citation Count126
Available for download26
Downloads (6 Weeks)75
Downloads (12 Months)874
Downloads (cumulative)7,244
Average downloads per article278.62
Average citations per article3.50
View colleagues of Koushik Chakraborty


Author image not provided  Gurindar S. Sohi

No contact information provided yet.

Bibliometrics: publication history
Publication years1985-2014
Publication count97
Citation Count2,793
Available for download68
Downloads (6 Weeks)91
Downloads (12 Months)1,482
Downloads (cumulative)36,792
Average downloads per article541.06
Average citations per article28.79
View colleagues of Gurindar S. Sohi

top of pageREFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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16 Citations

 
 
 
 
 
 
 
 

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The ACM Computing Classification System (CCS rev.2012)

Note: Larger/Darker text within each node indicates a higher relevance of the materials to the taxonomic classification.

top of pagePUBLICATION

· Proceeding
Title ASPLOS XIV Proceedings of the 14th international conference on Architectural support for programming languages and operating systems table of contents
General Chairs Mary Lou Soffa University of Virginia, USA
Program Chairs Mary Jane Irwin Penn State University, USA
Pages 169-180
Publication Date2009-03-07 (yyyy-mm-dd)
Sponsors SIGARCH ACM Special Interest Group on Computer Architecture
SIGOPS ACM Special Interest Group on Operating Systems
SIGPLAN ACM Special Interest Group on Programming Languages
ACM Association for Computing Machinery
PublisherACM New York, NY, USA ©2009
ISBN: 978-1-60558-406-5 Order Number: 415095 doi>10.1145/1508244.1508265
Conference ASPLOSArchitectural Support for Programming Languages and Operating Systems ASPLOS logo
Paper Acceptance Rate 29 of 113 submissions, 26%
Overall Acceptance Rate 503 of 2,475 submissions, 20%
Year Submitted Accepted Rate
ASPLOS VI 146 29 20%
ASPLOS VII 109 25 23%
ASPLOS VIII 123 28 23%
ASPLOS IX 114 24 21%
ASPLOS X 175 24 14%
ASPLOS XI 169 24 14%
ASPLOS XII 158 38 24%
ASPLOS XIII 127 31 24%
ASPLOS XIV 113 29 26%
ASPLOS XV 181 32 18%
ASPLOS XVI 152 32 21%
ASPLOS XVII 172 37 22%
ASPLOS '14 217 49 23%
ASPLOS '15 287 48 17%
ASPLOS '16 232 53 23%
Overall 2,475 503 20%
· Newsletter
Title ACM SIGARCH Computer Architecture News - ASPLOS 2009 table of contents archive
Volume 37 Issue 1, March 2009
Pages 169-180
Publication Date2009-03-01 (yyyy-mm-dd)
Sponsor SIGARCH ACM Special Interest Group on Computer Architecture
PublisherACM New York, NY, USA
ISSN: 0163-5964 doi>10.1145/2528521.1508265
· Newsletter
Title ACM SIGPLAN Notices - ASPLOS 2009 table of contents archive
Volume 44 Issue 3, March 2009
Pages 169-180
Publication Date2009-02-28 (yyyy-mm-dd)
Sponsor SIGPLAN ACM Special Interest Group on Programming Languages
PublisherACM New York, NY, USA
ISSN: 0362-1340 EISSN: 1558-1160 doi>10.1145/1508284.1508265

APPEARS IN
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Hardware Design
Networking
Software
Software
Performance
Performance
Performance

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top of pageTable of Contents

Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Table of Contents
Saving the Planet with Systems Research: Conference Keynote
Luiz Andre Barroso

The computing industry has become so successful that almost every economic sector benefits from its advances, while also being impacted by its costs. The energy footprint of computers is one such cost. The dramatic growth of computer deployments, both ...
expand
SESSION: Lessons learned and looking ahead
An evaluation of the TRIPS computer system
Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeff Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley
Pages: 1-12
doi>10.1145/1508244.1508246
Full text: PDFPDF

The TRIPS system employs a new instruction set architecture (ISA) called Explicit Data Graph Execution (EDGE) that renegotiates the boundary between hardware and software to expose and exploit concurrency. EDGE ISAs use a block-atomic execution model ...
expand
Architectural implications of nanoscale integrated sensing and computing
Constantin Pistol, Wutichai Chongchitmate, Christopher Dwyer, Alvin R. Lebeck
Pages: 13-24
doi>10.1145/1508244.1508247
Full text: PDFPDF

This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new computing domains and automate tasks that currently require expert scientific ...
expand
SESSION: Reliable systems I
CTrigger: exposing atomicity violation bugs from their hiding places
Soyeon Park, Shan Lu, Yuanyuan Zhou
Pages: 25-36
doi>10.1145/1508244.1508249
Full text: PDFPDF

Multicore hardware is making concurrent programs pervasive. Unfortunately, concurrent programs are prone to bugs. Among different types of concurrency bugs, atomicity violation bugs are common and important. Existing techniques to detect atomicity violation ...
expand
ASSURE: automatic software self-healing using rescue points
Stelios Sidiroglou, Oren Laadan, Carlos Perez, Nicolas Viennot, Jason Nieh, Angelos D. Keromytis
Pages: 37-48
doi>10.1145/1508244.1508250
Full text: PDFPDF

Software failures in server applications are a significant problem for preserving system availability. We present ASSURE, a system that introduces rescue points that recover software from unknown faults while maintaining both system integrity and availability, ...
expand
Recovery domains: an organizing principle for recoverable operating systems
Andrew Lenharth, Vikram S. Adve, Samuel T. King
Pages: 49-60
doi>10.1145/1508244.1508251
Full text: PDFPDF

We describe a strategy for enabling existing commodity operating systems to recover from unexpected run-time errors in nearly any part of the kernel, including core kernel components. Our approach is dynamic and request-oriented; it isolates the effects ...
expand
Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging
Martin Dimitrov, Huiyang Zhou
Pages: 61-72
doi>10.1145/1508244.1508252
Full text: PDFPDF

Software defects, commonly known as bugs, present a serious challenge for system reliability and dependability. Once a program failure is observed, the debugging activities to locate the defects are typically nontrivial and time consuming. In this paper, ...
expand
SESSION: Deterministic multiprocessing
Capo: a software-hardware interface for practical deterministic multiprocessor replay
Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas
Pages: 73-84
doi>10.1145/1508244.1508254
Full text: PDFPDF

While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on multiprocessors, while hardware-based proposals focus only on basic hardware-level ...
expand
DMP: deterministic shared memory multiprocessing
Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin
Pages: 85-96
doi>10.1145/1508244.1508255
Full text: PDFPDF

Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input, they can produce a different output. This frustrates debugging and limits ...
expand
Kendo: efficient deterministic multithreading in software
Marek Olszewski, Jason Ansel, Saman Amarasinghe
Pages: 97-108
doi>10.1145/1508244.1508256
Full text: PDFPDF

Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded applications, causes significant challenges for parallel programmers by ...
expand
SESSION: Prediction and accounting
Complete information flow tracking from the gates up
Mohit Tiwari, Hassan M.G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, Timothy Sherwood
Pages: 109-120
doi>10.1145/1508244.1508258
Full text: PDFPDF

For many mission-critical tasks, tight guarantees on the flow of information are desirable, for example, when handling important cryptographic keys or sensitive financial data. We present a novel architecture capable of tracking all information flow ...
expand
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
David K. Tam, Reza Azimi, Livio B. Soares, Michael Stumm
Pages: 121-132
doi>10.1145/1508244.1508259
Full text: PDFPDF

Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a shared-cache multicore processor. Obtaining L2 MRCs has generally been assumed ...
expand
Per-thread cycle accounting in SMT processors
Stijn Eyerman, Lieven Eeckhout
Pages: 133-144
doi>10.1145/1508244.1508260
Full text: PDFPDF

This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they are running simultaneously on the SMT processor. ...
expand
SESSION: Transactional memories
Maximum benefit from a minimal HTM
Owen S. Hofmann, Christopher J. Rossbach, Emmett Witchel
Pages: 145-156
doi>10.1145/1508244.1508262
Full text: PDFPDF

A minimal, bounded hardware transactional memory implementation significantly improves synchronization performance when used in an operating system kernel. We add HTM to Linux 2.4, a kernel with a simple, coarse-grained synchronization structure. The ...
expand
Early experience with a commercial hardware transactional memory implementation
Dave Dice, Yossi Lev, Mark Moir, Daniel Nussbaum
Pages: 157-168
doi>10.1145/1508244.1508263
Full text: PDFPDF

We report on our experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety ...
expand
SESSION: Reliable systems II
Mixed-mode multicore reliability
Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
Pages: 169-180
doi>10.1145/1508244.1508265
Full text: PDFPDF

Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly execute a single software thread, providing very high coverage from many ...
expand
ISOLATOR: dynamically ensuring isolation in comcurrent programs
Sriram Rajamani, G. Ramalingam, Venkatesh Prasad Ranganath, Kapil Vaswani
Pages: 181-192
doi>10.1145/1508244.1508266
Full text: PDFPDF

In this paper, we focus on concurrent programs that use locks to achieve isolation of data accessed by critical sections of code. We present ISOLATOR, an algorithm that guarantees isolation for well-behaved threads of a program that obey a locking discipline ...
expand
Efficient online validation with delta execution
Joseph Tucek, Weiwei Xiong, Yuanyuan Zhou
Pages: 193-204
doi>10.1145/1508244.1508267
Full text: PDFPDF

Software systems are constantly changing. Patches to fix bugs and patches to add features are all too common. Every change risks breaking a previously working system. Hence administrators loathe change, and are willing to delay even critical security ...
expand
SESSION: Power and storage in enterprise systems
PowerNap: eliminating server idle power
David Meisner, Brian T. Gold, Thomas F. Wenisch
Pages: 205-216
doi>10.1145/1508244.1508269
Full text: PDFPDF

Data center power consumption is growing to unprecedented levels: the EPA estimates U.S. data centers will consume 100 billion kilowatt hours annually by 2011. Much of this energy is wasted in idle systems: in typical deployments, server utilization ...
expand
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Adrian M. Caulfield, Laura M. Grupp, Steven Swanson
Pages: 217-228
doi>10.1145/1508244.1508270
Full text: PDFPDF

As our society becomes more information-driven, we have begun to amass data at an astounding and accelerating rate. At the same time, power concerns have made it difficult to bring the necessary processing power to bear on querying, processing, and understanding ...
expand
DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings
Aayush Gupta, Youngjae Kim, Bhuvan Urgaonkar
Pages: 229-240
doi>10.1145/1508244.1508271
Full text: PDFPDF

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage ...
expand
SESSION: Potpourri
Commutativity analysis for software parallelization: letting program transformations see the big picture
Farhana Aleen, Nathan Clark
Pages: 241-252
doi>10.1145/1508244.1508273
Full text: PDFPDF

Extracting performance from many-core architectures requires software engineers to create multi-threaded applications, which significantly complicates the already daunting task of software development. One solution to this problem is automatic compile-time ...
expand
Accelerating critical section execution with asymmetric multi-core architectures
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt
Pages: 253-264
doi>10.1145/1508244.1508274
Full text: PDFPDF

To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In multi-threaded applications, critical sections are used to ensure that only ...
expand
Producing wrong data without doing anything obviously wrong!
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney
Pages: 265-276
doi>10.1145/1508244.1508275
Full text: PDFPDF

This paper presents a surprising result: changing a seemingly innocuous aspect of an experimental setup can cause a systems researcher to draw wrong conclusions from an experiment. What appears to be an innocuous aspect in the experimental setup may ...
expand
SESSION: Managed systems
Leak pruning
Michael D. Bond, Kathryn S. McKinley
Pages: 277-288
doi>10.1145/1508244.1508277
Full text: PDFPDF

Managed languages improve programmer productivity with type safety and garbage collection, which eliminate memory errors such as dangling pointers, double frees, and buffer overflows. However, because garbage collection uses reachability to over-approximate ...
expand
Dynamic prediction of collection yield for managed runtimes
Michal Wegiel, Chandra Krintz
Pages: 289-300
doi>10.1145/1508244.1508278
Full text: PDFPDF

The growth in complexity of modern systems makes it increasingly difficult to extract high-performance. The software stacks for such systems typically consist of multiple layers and include managed runtime environments (MREs). In this paper, we investigate ...
expand
TwinDrivers: semi-automatic derivation of fast and safe hypervisor network drivers from guest OS drivers
Aravind Menon, Simon Schubert, Willy Zwaenepoel
Pages: 301-312
doi>10.1145/1508244.1508279
Full text: PDFPDF

In a virtualized environment, device drivers are often run inside a virtual machine (VM) rather than in the hypervisor, for reasons of safety and reduction in software engineering effort. Unfortunately, this approach results in poor performance for I/O-intensive ...
expand
SESSION: Architectures
Phantom-BTB: a virtualized branch target buffer design
Ioana Burcea, Andreas Moshovos
Pages: 313-324
doi>10.1145/1508244.1508281
Full text: PDFPDF

Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire ...
expand
StreamRay: a stream filtering architecture for coherent ray tracing
Karthik Ramani, Christiaan P. Gribble, Al Davis
Pages: 325-336
doi>10.1145/1508244.1508282
Full text: PDFPDF

The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-buffer algorithm and provide a highly interactive experience at a relatively ...
expand
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Robert D. Cameron, Dan Lin
Pages: 337-348
doi>10.1145/1508244.1508283
Full text: PDFPDF

Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF-8 to UTF-16 transcoding, XML parsing, string search and regular expression matching. ...
expand

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