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A novel sequential circuit optimization with clock gating logic

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Authors: Yu-Min Kuo National Tsing Hua University, Hsinchu, Taiwan
Shih-Hung Weng National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang National Tsing Hua University, Hsinchu, Taiwan
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· Proceeding
ICCAD '08 Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Press Piscataway, NJ, USA ©2008
table of contents ISBN: 978-1-4244-2820-5
A novel sequential circuit optimization with clock gating logic 2008 Article
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· Citation Count: 2


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