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The effect of design parameters on single-event upset sensitivity of MOS current mode logic
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Authors:
Mahta Haghi
University of Southern California, Los Angeles, CA, USA
Jeff Draper
University of Southern California, Marina Del Rey, CA, USA
Published in:
· Proceeding
GLSVLSI '09
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-522-2
doi>
10.1145/1531542.1531599
2009 Article
Short paper
Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 7
· Citation Count: 0
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Tags:
design
design parameters
mos current mode logic
performance
radiation hardening
reliability
single event upset
vlsi
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