Spatial and temporal design debug using partial MaxSAT

doi:10.1145/1531542.1531621

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Spatial and temporal design debug using partial MaxSAT

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Authors:	Yibin Chen	University of Toronto, Toronto, ON, Canada
	Sean Safarpour	University of Toronto, Toronto, ON, Canada
	Andreas Veneris	University of Toronto, Toronto, ON, Canada
	Joao Marques-Silva	University of Southampton, Southampton, Gt Britain

	2009 Article
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	GLSVLSI '09 Proceedings of the 19th ACM Great Lakes symposium on VLSI
	ACM New York, NY, USA ©2009 table of contents ISBN: 978-1-60558-522-2 doi>10.1145/1531542.1531621

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Tags: algorithms computer-aided design design debugging maximum satisfiability verification

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