A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

doi:10.1145/1531542.1531630

A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

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Authors:	Marshnil Vipin Dave	IIT-Bombay, Mumbai, India
	Maryam Shojaei Baghini	IIT-Bombay, Mumbai, India
	Dinesh Kumar Sharma	IIT-Bombay, Mumbai, India

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	GLSVLSI '09 Proceedings of the 19th ACM Great Lakes symposium on VLSI
	ACM New York, NY, USA ©2009 table of contents ISBN: 978-1-60558-522-2 doi>10.1145/1531542.1531630

	2009 Article Poster
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Tags: current mode singnaling design dynamic overdriving input/output circuits microprocessors and microcomputers performance process variation tolerant vlsi

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