Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)

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Authors:	Stephen Roderick Hines	NVIDIA Corporation, Santa Clara, CA, USA
	Yuval Peress	Florida State University, Tallahassee, FL, USA
	Peter Gavin	Florida State University, Tallahassee, FL, USA
	David Whalley	Florida State University, Tallahassee, FL, USA
	Gary Tyson	Florida State University, Tallahassee, FL, USA

	2009 Article
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	· Proceeding
	LCTES '09 Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
	Pages 119-128 ACM New York, NY, USA ©2009 table of contents ISBN: 978-1-60558-356-3 doi>10.1145/1542452.1542469
	· Newsletter
	ACM SIGPLAN Notices - LCTES '09
	Volume 44 Issue 7, July 2009 Pages 119-128 ACM New York, NY, USA table of contents doi>10.1145/1543136.1542469

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Tags: experimentation l0/filter cache lookahead instruction fetch engine measurement performance processor architectures tagless hit instruction cache