SIGN IN
SIGN UP
Predicting the worst-case voltage violation in a 3D power network
Full Text:
Pdf
Buy this Article
Authors:
Wanping Zhang
Qualcomm Inc., San Diego, CA, USA and UC San Diego, La Jolla, CA, USA
Wenjian Yu
Tsinghua University, Beijing, China
Xiang Hu
UC San Diego, La Jolla, CA, USA
Amirali Shayan
UC San Diego, La Jolla, CA, USA
A. Ege Engin
San Diego State University, San Diego, CA, USA
Chung-Kuan Cheng
UC San Diego, La Jolla, CA, USA
2009 Article
Bibliometrics
· Downloads (6 Weeks): 0
· Downloads (12 Months): 8
· Downloads (cumulative): 131
· Citation Count: 0
Published in:
· Proceeding
SLIP '09
Proceedings of the 11th international workshop on System level interconnect prediction
Pages 93-98
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-576-5
doi>
10.1145/1572471.1572487
Tools and Resources
Buy this Article
Request Permissions
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
SLIP '13
Share:
|
Tags:
algorithms
clock gating
computer-aided design
design
integer linear programming
leakage
performance
performance analysis and design aids
power networks
worst case violation prediction
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder