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Reliable non-zero skew clock trees using wire width optimization
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Authors:
Satyamurthy Pullela
Noel Menezes
Lawrence T. Pillage
Published in:
· Proceeding
DAC '93 Proceedings of the 30th international Design Automation Conference
Pages 165-170
ACM
New York, NY
, USA
©1993
table of contents
ISBN:0-89791-577-1
doi>
10.1145/157485.164653
1993 Article
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· Citation Count: 31
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algorithms
design
placement and routing
routing and layout
trees
vlsi
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