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Memory models: a case for rethinking parallel languages and hardware
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Author:
Sarita V. Adve
University of Illinois at Urbana-Champaign, Urbana, IL, USA
Published in:
· Proceeding
SPAA '09
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-606-9
doi>
10.1145/1583991.1584005
2009 Article
Keynote
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· Downloads (12 Months): 31
· Citation Count: 0
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SPAA '12
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concurrent programming structures
design
languages
memory consistency models
memory models
multicore architecture
parallel architectures
performance
reliability
safe programming
standardization
verification
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