REDEFINE: Runtime reconfigurable polymorphic ASIC

doi:10.1145/1596543.1596545

REDEFINE: Runtime reconfigurable polymorphic ASIC

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Authors:	Mythri Alle	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Keshavan Varadarajan	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Alexander Fell	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Ramesh Reddy C.	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Nimmy Joseph	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Saptarsi Das	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Prasenjit Biswas	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Jugantor Chetia	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Adarsh Rao	CAD Lab, SERC, Indian Institute of Science, Bangalore
	S. K. Nandy	CAD Lab, SERC, Indian Institute of Science, Bangalore
	Ranjani Narayan	Morphing Machines, Bangalore, India

	2009 Article Research Refereed
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	ACM Transactions on Embedded Computing Systems (TECS) TECS Homepage archive
	Volume 9 Issue 2, October 2009 Article No. 11 ACM New York, NY, USA table of contents doi>10.1145/1596543.1596545

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Tags: application synthesis custom instruction extension dataflow software pipeline design honeycomb noc other architecture styles polymorphic asic router runtime reconfiguration

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