A methodology for tuning two-level cache hierarchy considering energy and performance

doi:10.1145/1601896.1601905

A methodology for tuning two-level cache hierarchy considering energy and performance

Full Text:

PDF

Buy this Article

Authors:	A. G. Silva-Filho	Federal University of Pernambuco (UFPE), Recife - PE, Brazil
	C. C. Araújo	Federal University of Pernambuco (UFPE), Recife - PE, Brazil

Published in:

	· Proceeding
	SBCCI '09 Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
	ACM New York, NY, USA ©2009 table of contents ISBN: 978-1-60558-705-9 doi>10.1145/1601896.1601905

	2009 Article
Bibliometrics
· Downloads (6 Weeks): 0 · Downloads (12 Months): 19 · Citation Count: 0

Tools and Resources

Buy this Article
Request Permissions
TOC Service:
- Email
- RSS
Save to Binder
Export Formats:
- BibTeX
- EndNote
- ACM Ref

Tags: cache memories embedded systems exploration mechanism low power design memory hierarchy system-on-chip two-level caches

The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2012 ACM, Inc.
Terms of Usage Privacy Policy Code of Ethics Contact Us

Useful downloads:

Adobe Acrobat

QuickTime

Windows Media Player

Real Player