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Reliability aware yield improvement technique for nanotechnology based circuits
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Authors:
C. Argyrides
University of Bristol, Bristol, UK
G. Dimosthenous
University of Bristol, Bristol, UK
D. K. Pradhan
University of Bristol, Bristol, UK
C. A. Lisboa
Instituto de Informática, PPGC, UFRGS, Porto Alegre -- RS - Brazil
L. Carro
Instituto de Informática, PPGC, UFRGS, Porto Alegre -- RS - Brazil
2009 Article
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Published in:
· Proceeding
SBCCI '09
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Article No. 48
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-705-9
doi>
10.1145/1601896.1601958
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design
economics
nanotechnology
reliability
reliability
yield improvement
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