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Functional verification of power gate design in SystemC RTL
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Authors:
George Sobral Silveira
Universidade Federal de Campina Grande, Campina Grande, PB - Brazil
Alisson Vasconcelos Brito
Universidade Federal da Paraíba, Center Rio Tinto, PB - Brazil
Elmar U. K. Melcher
Universidade Federal de Campina Grande, Campina Grande, PB - Brazil
Published in:
· Proceeding
SBCCI '09
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Article No. 52
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-705-9
doi>
10.1145/1601896.1601963
2009 Article
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· Citation Count: 2
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Tags:
functional verification
power gate
register-transfer-level implementation
rtl
simulation
systemc
verification
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