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State assignment for hardwired VLSI control units
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Author:
Bernhard Eschermann
Published in:
· Journal
ACM Computing Surveys (CSUR)
Surveys Homepage
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Volume 25 Issue 4, Dec. 1993
Pages 415-436
ACM
New York, NY
, USA
table of contents
doi>
10.1145/162124.162132
1993 Article
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· Downloads (12 Months): 22
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· Citation Count: 1
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Tags:
algorithms
automatic synthesis
built-in tests
coding constraints
computer-aided design
control design
design
finite-state machines
integrated circuits
logic design
sequential circuits
state assignment
synthesis
testability
vlsi
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