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Exploiting residue number system for power-efficient digital signal processing in embedded processors
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Authors:
Rooju Chokshi
Arizona State University, Tempe, AZ, USA
Krzysztof S. Berezowski
Arizona State University, Tempe, AZ, USA
Aviral Shrivastava
Arizona State University, Tempe, AZ, USA
Stanislaw J. Piestrak
Université Paul Verlaine - Metz, --, France
2009 Article
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· Proceeding
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Pages 19-28
ACM
New York, NY
, USA
©2009
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ISBN: 978-1-60558-626-7
doi>
10.1145/1629395.1629401
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Tags:
algorithms
compiler
design
microprocessor/microcomputer applications
per-
performance
pipeline processors
power
processor
residue number system
risc/cisc, vliw architectures
signal processing systems
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