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Clock skew optimization via wiresizing for timing sign-off covering all process corners
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Authors:
Sari Onaissi
University of Toronto, Canada
Khaled R. Heloue
University of Toronto, Canada
Farid N. Najm
University of Toronto, Canada
Published in:
· Proceeding
DAC '09
Proceedings of the 46th Annual Design Automation Conference
ACM
New York, NY
, USA
©2009
table of contents
ISBN: 978-1-60558-497-3
doi>
10.1145/1629911.1629964
2009 Article
Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 23
· Citation Count: 0
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Upcoming Conference:
DAC '12
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Tags:
algorithms
clock skew optimization
design aids
parameterized timing analysis
performance
reliability
sign-off
variability
verification
wiresizing
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