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No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips

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Authors:	Shu-Hsuan Chou	National Chung Cheng University, Taiwan, R.O.C.
	Chien-Chih Chen	National Chung Cheng University, Taiwan, R.O.C.
	Chi-Neng Wen	National Chung Cheng University, Taiwan, R.O.C.
	Yi-Chao Chan	National Chung Cheng University, Taiwan, R.O.C.
	Tien-Fu Chen	National Chung Cheng University, Taiwan, R.O.C.
	Chao-Ching Wang	National Chung Cheng University, Taiwan, R.O.C.
	Jinn-Shyan Wang	National Chung Cheng University, Taiwan, R.O.C.

	2009 Article
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DAC '09 Proceedings of the 46th Annual Design Automation Conference

ACM New York, NY, USA ©2009
table of contents ISBN: 978-1-60558-497-3 doi>10.1145/1629911.1630062

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Tags: arbitration design level-1 non-uniform cache architecture management memory structure multi-core multiple data stream architectures noc parallel architectures performance ring interconnection single-cycle transactions soc topology

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