FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

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Authors: Scott Cromar University of Illinois, Urbana-Champaign
Jaeho Lee University of Illinois, Urbana-Champaign
Deming Chen University of Illinois, Urbana-Champaign
Published in:
· Proceeding
DAC '09 Proceedings of the 46th Annual Design Automation Conference
Pages 838-843
ACM New York, NY, USA ©2009
table of contents ISBN: 978-1-60558-497-3 doi>10.1145/1629911.1630125
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation Published by ACM 2009 Article
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