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Optimum LDPC decoder: a memory architecture problem
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Authors:
Erick Amador
EURECOM, Sophia Antipolis, France
Renaud Pacalet
TELECOM ParisTech, Sophia Antipolis
Vincent Rezard
Infineon Technologies France, Sophia Antipolis
Published in:
· Proceeding
DAC '09
Proceedings of the 46th Annual Design Automation Conference
ACM
New York, NY
, USA
©2009
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ISBN: 978-1-60558-497-3
doi>
10.1145/1629911.1630141
2009 Article
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· Downloads (12 Months): 23
· Citation Count: 0
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algorithms
design
design styles
ldpc codes
low power architectures
memory optimization
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