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Router designs for elastic buffer on-chip networks
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Authors:
George Michelogiannakis
Stanford University, Stanford, CA
William J. Dally
Stanford University, Stanford, CA
Published in:
· Proceeding
SC '09
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Article No. 2
ACM
New York, NY
, USA
©2009
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ISBN: 978-1-60558-744-8
doi>
10.1145/1654059.1654062
2009 Article
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· Downloads (12 Months): 23
· Downloads (cumulative): 295
· Citation Count: 3
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SC '13
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interconnection architectures
interconnections
on-chip networks
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