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Scalable parallel memory architecture with a skew scheme
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Authors:
Tadayuki Sakakibara
Katsuyoshi Kitai
Tadaaki Isobe
Shigeko Yazawa
Teruo Tanaka
Yasuhiro Inagami
Yoshiko Tamaki
1993 Article
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Published in:
· Proceeding
ICS '93 Proceedings of the 7th international conference on Supercomputing
Pages 157 - 166
ACM
New York, NY
, USA
©1993
table of contents
ISBN:0-89791-600-X
doi>
10.1145/165939.165966
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design
illiac iv
instruction set design
parallel processors
performance
super computers
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