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A scalar architecture for pseudo vector processing based on slide-windowed registers
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Authors:
Hiroshi Nakamura
Taisuke Boku
Hideo Wada
Hiromitsu Imori
Ikuo Nakata
Yasuhiro Inagami
Kisaburo Nakazawa
Yoshiyuki Yamashita
1993 Article
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Published in:
· Proceeding
ICS '93 Proceedings of the 7th international conference on Supercomputing
Pages 298 - 307
ACM
New York, NY
, USA
©1993
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ISBN:0-89791-600-X
doi>
10.1145/165939.165998
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arithmetic and logic units
array and vector processors
design
modeling techniques
performance
performance attributes
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