An hybrid eDRAM/SRAM macrocell to implement first-level data caches

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Authors: Alejandro Valero Universidad Politécnica de Valencia, Valencia, Spain
Julio Sahuquillo Universidad Politécnica de Valencia, Valencia, Spain
Salvador Petit Universidad Politécnica de Valencia, Valencia, Spain
Vicente Lorente Universidad Politécnica de Valencia, Valencia, Spain
Ramon Canal Universitat Politècnica de Catalunya, Barcelona, Spain
Pedro López Universidad Politécnica de Valencia, Valencia, Spain
José Duato Universidad Politécnica de Valencia, Valencia, Spain
An hybrid eDRAM/SRAM macrocell to implement first-level data caches Published by ACM 2009 Article
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MICRO 42 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Pages 213-221
ACM New York, NY, USA ©2009
table of contents ISBN: 978-1-60558-798-1 doi>10.1145/1669112.1669140

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