A distributed shared memory multiprocessor ASURA: memory and cache architecture

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Authors: S. Mori Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan
H. Saito Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan
M. Goshima Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan
S. Tomita Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan
M. Yanagihara KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan
T. Tanaka KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan
D. Fraser KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan
K. Joe KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan
H. Nitta KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan
A distributed shared memory multiprocessor ASURA: memory and cache architecture Published by ACM 1993 Article
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Published in:
· Proceeding
Supercomputing '93 Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Pages 740-749
ACM New York, NY, USA ©1993
table of contents ISBN:0-8186-4340-4 doi>10.1145/169627.169825

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