A parallel block implementation of Level-3 BLAS for MIMD vector processors

Full Text: PDFPDF Buy this ArticleBuy this Article
Authors: Michel J. Daydé ENSEEIHT-IRIT, Toulouse, France
Iain S. Duff CERFACS, Toulouse, France
Antoine Petitet CERFACS, Toulouse, France
Published in:
· Journal
ACM Transactions on Mathematical Software (TOMS) TOMS Homepage archive
Volume 20 Issue 2, June 1994
Pages 178-193
ACM New York, NY, USA
table of contents doi>10.1145/178365.174413
A parallel block implementation of Level-3 BLAS for MIMD vector processors Published by ACM 1994 Article
Bibliometrics Data  Bibliometrics
· Downloads (6 Weeks): 2
· Downloads (12 Months): 13
· Downloads (cumulative): 365
· Citation Count: 4


Tools and Resources

Share:

|
feedback Feedback | Switch to single page view (no tabs)

Powered by The ACM Guide to Computing Literature


The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2013 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player
The ACM Guide to Computing Literature
All Tags
Export Formats
 
 
Save to Binder