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Write activity reduction on flash main memory via smart victim cache
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Authors:
Liang Shi
University of Science and Technology of China, Hefei, China
Chun Jason Xue
City University of Hong Kong, Kowloon, Hong Kong
Jingtong Hu
University of Texas at Dallas, Richardson, TX, 75080, Dallas, TX, USA
Wei-Che Tseng
University of Texas at Dallas, Richardson, TX, 75080, Dallas, TX, USA
Xuehai Zhou
University of Science and Technology of China, Hefei, China
Edwin H.-M. Sha
University of Texas at Dallas, Richardson, TX, 75080, Dallas, USA
2010 Article
Poster
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· Citation Count: 5
Published in:
· Proceeding
GLSVLSI '10
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Pages 91-94
ACM
New York, NY
, USA
©2010
table of contents
ISBN: 978-1-4503-0012-4
doi>
10.1145/1785481.1785503
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Tags:
cache
cache memories
design
experimentation
main memory
nand flash memory
performance
primary memory
victim cache
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