SIGN IN
SIGN UP
Process-induced skew variation for scaled 2-D and 3-D ICs
Full Text:
PDF
Buy this Article
Authors:
Hu Xu
LSI-EPFL, Lausanne, Switzerland
Vasilis F. Pavlidis
LSI-EPFL, Lausanne, Switzerland
Giovanni De Micheli
LSI-EPFL, Lausanne, Switzerland
Published in:
· Proceeding
SLIP '10
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Pages 17-24
ACM
New York, NY
, USA
©2010
table of contents
ISBN: 978-1-4503-0037-7
doi>
10.1145/1811100.1811107
2010 Article
Bibliometrics
· Downloads (6 Weeks): 0
· Downloads (12 Months): 18
· Downloads (cumulative): 129
· Citation Count: 1
Tools and Resources
Buy this Article
Request Permissions
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
SLIP '13
Share:
|
Tags:
3-d ics
clock distribution networks
clock skew
performance
process variations
reliability
technology scaling
vlsi
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder