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Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors
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Authors:
Claude-Pierre Jeannerod
Université de Lyon, France
Christophe Mouilleron
Université de Lyon, France
Jean-Michel Muller
Université de Lyon, France
Guillaume Revy
Université de Lyon, France
Christian Bertin
STMicroelectronics Compilation Expertise Center, Grenoble, France
Jingyan Jourdan-Lu
STMicroelectronics Compilation Expertise Center, Grenoble, France
Hervé Knochel
STMicroelectronics Compilation Expertise Center, Grenoble, France
Christophe Monat
STMicroelectronics Compilation Expertise Center, Grenoble, France
2010 Article
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Published in:
· Proceeding
PASCO '10
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
ACM
New York, NY
, USA
©2010
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ISBN: 978-1-4503-0067-4
doi>
10.1145/1837210.1837212
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Tags:
algorithm design and analysis
algorithms
binary floating-point arithmetic
c software implementation
code generation
code generation
compilers
computer arithmetic
correct rounding
design
ieee 754
instruction-level parallelism
parallel algorithms
parallel and vector implementations
performance
polynomial evaluation
reliability
standards
vliw processor
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