0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

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Authors: Yohei Nakata Kobe University, Kobe, Japan
Shunsuke Okumura Kobe University, Kobe, Japan
Hiroshi Kawaguchi Kobe University, Kobe, Japan
Masahiko Yoshimoto Kobe University and JST,CREST, Kobe, Japan
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM Published by ACM 2010 Article
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ISLPED '10 Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Pages 219-224
ACM New York, NY, USA ©2010
table of contents ISBN: 978-1-4503-0146-6 doi>10.1145/1840845.1840888

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